This invention relates generally to semiconductor memories, and more particularly, to the improvement of soft error rate through the addition of high resistor cell structures.
Semiconductor memories are composed of large arrays of individual cells. Each cell stores a 1 or 0 bit of data as an electrical high or low voltage state. At least 8 bits may compose a byte of data. At least 16 bits may compose a word. In each memory operation cycle, at least one byte is typically written into or read from the array. Cells are arranged at the crossings of vertical data, or bit lines, and horizontal word lines, which enable reading or writing. A read or write cycle occurs when a word line, as well as a pair of bit lines, are activated. The cell accessed at the intersection of the word lines and the bit lines will either receive written data from the bit lines, or will deliver written data to the bit lines. Cells can typically be accessed in random order.
A cell is composed of an electronic circuit, typically involving transistors. A Static Random Access Memory (SRAM) cell is most typically composed of a plurality of metal-oxide-semiconductor field-effect-transistors (MOSFETs). The most common type of SRAM is composed of six-transistor (6T) cells, each of which includes two P-type MOSFETs (PMOSFETs) and four N-type MOSFETs (NMOSFETs). A cell is arranged with two inverters that are accessed from two complementary bit lines through two access transistors that are controlled by a word line. This structure has low power consumption and good immunity to electronic noise on bit or word lines or to charges introduced by alpha particles.
However, as more technologies that utilize semiconductor memories require a smaller footprint and a higher mobility, space saving in semiconductor memory designs becomes increasingly important. In particular, in order to continually achieve size and performance advantages, cell geometries must continually shrink. However, as cell geometries shrink, one problem arises. Each of the two inverter storage nodes in an SRAM cell is composed of the capacitances of the gates of the two transistors of that inverter. As geometries shrink, the storage capacitances also shrink. The charge, which is stored as data, is now so small that electrical noise on either of the bit lines or the word lines, or charges introduced by the arrival of an alpha particle, can be significant in comparison. The frequency of error caused by this electrical noise, which may be in the form of alpha particles, is known as soft error rate. As soft error rate increases, the risk of losing data integrity increases. Noise immunity, therefore, is an area in semiconductor memory designs that merits increasing concern.
Desirable in the art of semiconductor memory designs are additional designs that increases noise immunity, thereby reducing soft error rate.